The present invention relates to semiconductor devices.
Unlike a hard error which is permanent destruction of a specific portion of a circuit, a soft error is a recoverable fleeting malfunction which occurs in a semiconductor chip. The soft error is caused by incidence of a neutron ray among secondary cosmic rays, an alpha ray from the packaging material of a Large Scale Integration (LSI), or a like ray on the LSI.
Various countermeasures against the soft error are devised. One effective and general countermeasure is a method of designing a circuit which prevents a system from being affected by such an error. For example, an Error Correction Code (ECC) circuit is capable of correcting an error. Such countermeasures are accompanied by an increase in the area of an LSI and are not applicable to every logic circuit.
FIG. 1 shows other soft error avoiding means. A capacitor 1203 is added to a data holding node of a latch circuit having inverters 1201 and 1202 in order to suppress data inversion caused by occurrence of electric charge due to radiation. This case results in performance degradations including prolonged setup time and delay time.
Another known technique is a master-slave flip-flop circuit as described below. The master-slave flip-flop circuit includes a master-side closed loop circuit including a first switching element configured to perform data input control, a plurality of semiconductor elements, and second and third switching elements configured to control the holding of input data inputted through the first switching element, and a slave-side closed loop circuit including a plurality of semiconductor elements inclusive of some of the semiconductor elements, and a fourth switching element configured to control the holding of the input data.
Yet another known technique is an inverter as described below. The inverter has a doubled structure wherein a first p-channel metal oxide semiconductor (MOS) transistor and a first n-channel MOS transistor are coupled in series with a source or drain line in this order from a node coupled to a first voltage source side toward a node coupled to a second voltage source side; and a second MOS transistor which is gate-to-gate coupled to at least one of the first p-channel MOS transistor and the first n-channel MOS transistor and which has the same conductivity type channel as that transistor is further coupled in series with the source or drain line.